1. Field of the Invention
The present disclosure generally relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a novel contact structure for a semiconductor device, such as SRAM memory devices, and various methods of making such a contact structure.
2. Description of the Related Art
Semiconductor memory devices are in widespread use in many modern integrated circuit devices and in many consumer products. In general, memory devices are the means by which electrical information is stored. There are many types of memory devices, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), ROMs (Read Only Memory), etc., each of which has its own advantages and disadvantages relative to other types of memory devices. For example, SRAMs are typically employed in applications where higher speed and/or reduced power consumption is important, e.g., the cache memory of a microprocessor, mobile phones and other mobile consumer products, etc. Millions of such memory devices are typically included in even very basic electronic consumer products. Irrespective of the type of memory device, there is a constant drive in the industry to increase the performance and durability of such memory devices. In typical operations, an electrical charge (HIGH) is stored in the memory device to represent a digital “1”, while the absence of such an electrical charge or a relatively low charge (LOW) stored in the device indicates a digital “0”. Special read/write circuitry is used to access the memory device to store digital information on such a memory device and to determine whether or not a charge is presently stored in the memory device. These program/erase cycles (“P/E cycles”) typically occur millions of times for a single memory device over its effective lifetime.
In general, efforts have been made to reduce the physical size of such memory devices, particularly reducing the physical size of components of the memory devices, such as transistors, to increase the density of memory devices, thereby increasing performance and decreasing the costs of the integrated circuits incorporating such memory devices. Increases in the density of the memory devices may be accomplished by forming smaller structures within the memory device and by reducing the separation between the memory devices and/or between the structures that make up the memory device. Often, these smaller design rules are accompanied by layout, design and architectural modifications which are either made possible by the reduced sizes of the memory device or its components, or such modifications are necessary to maintain performance when such smaller design rules are implemented. As an example, the reduced operating voltages used in many modern-day conventional integrated circuits are made possible by improvements in design, such as reduced gate insulation thicknesses in the component transistors and improved tolerance controls in lithographic processing. On the other hand, reduced design rules make reduced operating voltages essential to limit the effects of hot carriers generated in small size devices operating at higher, previously conventional operating voltages.
Making SRAMs in accordance with smaller design rules, as well as using reduced internal operating voltages, can reduce the stability of SRAM cells. Reduced operating voltages and other design changes can reduce the voltage margins which ensure that an SRAM cell remains in a stable data state during a data read operation, increasing the likelihood that the read operation could render indeterminate or lose entirely the data stored in the SRAM cell.
FIGS. 1A-1D depict various aspects of an illustrative prior art SRAM device 10. As shown in FIG. 1A, a typical 6T (six transistors) SRAM memory cell 10 includes two NMOS access or “pass gate” transistors AT1, AT2, two PMOS “pull-up” transistors P1, P2, and two NMOS “pull-down” transistors N1, N2. Each of the PMOS pull-up transistors P1, P2 has its gate connected to the gate of a corresponding NMOS pull-down transistor N1, N2. The drains of the PMOS pull-up transistors P1, P2 have their drains connected to the drains of corresponding NMOS pull-down transistors N1, N2 to form inverters having the conventional configuration. The sources of the PMOS pull-up transistors P1, P2 are connected to a high reference potential, typically VCC, and the sources of the NMOS pull-down transistors N1, N2 are connected to a lower reference potential, typically VSS or ground. The gates of the PMOS pull-up transistor P1 and the NMOS pull-down transistor N1, which make up one inverter, are connected to the drains of the transistors P2, N2 of the other inverter. Similarly, the gates of the PMOS pull-up transistor P2 and the NMOS pull-down transistor N2, which make up the other inverter, are connected to the drains of the transistors P1, N1. Hence, the potential present on the drains of the transistors P1, N1 (node NA) of the first inverter is applied to the gates of transistors P2, N2 of the second inverter and the charge serves to keep the second inverter in an ON or OFF state. The logically opposite potential is present on the drains of the transistors P2, N2 (node NB) of the second inverter and on the gates of the transistors P1, N1 of the first inverter, keeping the first inverter in the complementary OFF or ON state relative to the second inverter. Thus, the latch of the illustrated SRAM cell 10 has two stable states: a first state with a predefined potential present on charge storage node NA and a low potential on charge storage node NB; and a second state with a low potential on charge storage node NA and the predefined potential on charge storage node NB. Binary data are recorded by toggling between the two states of the latch. Sufficient charge must be stored on the charge storage node, and thus on the coupled gates of the associated inverter, to unambiguously hold one of the inverters “ON” and unambiguously hold the other of the inverters “OFF”, thereby preserving the memory state. The stability of an SRAM cell 10 can be quantified by the margin by which the potential on the charge storage nodes can vary from its nominal value while still keeping the SRAM 10 cell in its original state.
Data is read out of the conventional SRAM cell 10 in a non-destructive manner by selectively coupling each charge storage node (NA, NB) to a corresponding one of a pair of complementary bit lines (BL, BL). The selective coupling is accomplished by the aforementioned access transistors AT1, AT2, where each access transistor is connected between one of the charge storage nodes (NA, NB) and one of the complementary bit lines (BL, BL). Word line signals are provided to the gates of the access transistors AT1, AT2 to switch the access transistors ON during data read operations. Charge flows through the ON access transistors to or from the charge storage nodes (NA, NB), discharging one of the bit lines and charging the other of the bit lines. The voltage changes on the bit lines are sensed by a differential amplifier (not shown).
Prior to a read out operation, the bit lines BL, BL are typically equalized at a voltage midway between the high and low reference voltages, typically ½ (VCC−VSS), and then a signal on the word line WL turns the access transistors AT1, AT2 ON. As an example, consider that NA is charged to a predetermined potential of VCC and NB is charged to a lower potential VSS. When the access transistors AT1, AT2 turn ON, charge begins flowing from node NA through access transistor AT1 to bit line BL. The charge on node NA begins to drain off to the bit line BL and is replenished by charge flowing through pull-up transistor P1 to node NA. At the same time, charge flows from bit line BL through pass gate transistor AT2 to node NB and the charge flows from the node NB through the pull-down transistor N2. To the extent that more current flows through pass gate transistor AT1 than flows through pull-up transistor P1, charge begins to drain from the node NA, which, on diminishing to a certain level, can begin turning OFF pull-down transistor N2. To the extent that more current flows through pass gate transistor AT2 than flows through pull-down transistor N2, charge begins to accumulate on charge storage node NB, which, on charging to a certain level, can begin turning OFF pull-up transistor P1. For the SRAM cell's latch to remain stable during such a data reading operation, at least one of the charge storage nodes (NA, NB) within the SRAM cell 10 must charge or discharge at a faster rate than charge flows from or to the corresponding bit line.
FIG. 1B is a plan view of an illustrative prior art SRAM device 10 at an early stage of manufacture. The SRAM device 10 is generally comprised of a pair of illustrative N-type pull-down transistors N1, N2, a pair of illustrative P-type pull-up transistors P1, P2 and a pair of N-type access or pass gate transistors AT1, AT2. The SRAM device 10 includes a plurality of conductive gate structures 20, 22, 24 and 26 that are formed above various active regions 14, 16, 18 and 19. The active regions 14, 16, 18 and 19 are defined in a semiconducting substrate 10 (not shown in FIG. 1B) by illustrative isolation regions 12. Note that the gate structure 22 serves as a shared gate electrode for both of the transistors N1 and P1, while the gate structure 24 serves as a shared gate electrode for both of the transistors N2 and P2. An illustrative sidewall spacer 23 has been formed adjacent each of the gate structures 20, 22, 24 and 26. Although not depicted in FIG. 1B, at this point in the process flow, a plurality of source/drain implant regions 27 have been formed in the active regions 20, 22, 24 and 26, as shown in FIG. 1D. The schematically depicted source/drain regions 27 were formed by performing traditional ion implantation techniques, e.g., by performing an initial extension implant process, followed by forming the spacer 23, and then by performing a deep source/drain implant process.
FIG. 1C depicts the prior art SRAM device 10 after a plurality of conductive contact structures have been formed for the device. More specifically, the SRAM device 10 includes a plurality of conductive contacts CA1-CA3 that conductively contact active region 14, CA4 that conductively contacts active region 16, CA5 that conductively contacts active region 18, and CA6-CA8 that conductively contact active region 19. Also depicted in FIG. 1C is a plurality of so-called CAREC (“CA-Rectangular”) contacts, CAREC 1-4. The unit cell of an SRAM 10 only includes two CAREC contacts—CAREC-2 and CAREC-3. The various conductive contact structures shown in FIG. 1C may be formed from traditional materials using traditional techniques for forming such conductive contacts, e.g., damascene type techniques, etc.
FIG. 1D is a cross-sectional view taken where indicated in FIG. 1C. The representative gate structure 22 is comprised of a thermally grown layer of silicon dioxide 30 and a polysilicon gate electrode 31. In general, the CAREC contact structures are dual contact structures. For example, as shown in FIG. 1D, the CAREC-3 structure is conductively coupled to the upper surface 31U and end surface 31E of the gate electrode 31 and to the surface 18S of the active region 18. The use of such CAREC contact structures has become popular due to the increasing demands for greater packing densities on integrated circuit products, i.e., the use of such CAREC contact structures enables the production of more densely packed devices.
Although the use of such CAREC contact structures is widespread, such use is not without problems. For example, the difference in physical size between the CAREC contacts and the other CA contacts may adversely affect the formation of the contact openings as, in general, a larger opening tends to etch at a faster rate than a smaller opening. Such size differences may also adversely impact the formation of the conductive materials in the various contact openings as the aspect ratio for the CA contacts is generally larger than the aspect ratio of the CAREC contacts. Additionally, with the current CAREC formation process and structure, there is a relatively undoped region 21 in the active region under the end 31A of the gate electrode 31. This undoped region 21 provides a ready leakage path and may result in the device having unacceptable levels of leakage current.
The present disclosure is directed towards a novel contact structure for semiconductor devices, such as SRAM memory devices, that may avoid, or at least reduce, the effects of one or more of the problems identified above.